Pt Gate Sink-In Process Details Impact on InP HEMT DC and RF Performance

A Pt/Ti/Pt/Au gate electrode stack is commonly used in AlInAs/GaInAs/InP high electron mobility transistors due to the high Schottky barrier height of Pt on AlInAs and the fact that Pt can be controllably diffused through semiconductor layers thereby enabling vertical scaling. We show here that the Pt-AlInAs reaction is not only controlled by the annealing time and temperature-the annealing ambient and the thermal ramp rate also affect the diffusion of Pt through the underlying semiconductor layers and impact the DC and RF device performance. Following the gate metal deposition, one process split was rapid thermal annealed at 250 °C and subsequently passivated by atomic layer deposition (ALD) at 180 °C. For the second process split, the Pt gate sink-in process was carried out in the ALD system at 250 °C simultaneously with the gate passivation. Despite identical gate sink-in temperatures, the two process splits exhibit different characteristics suggesting different gate-to-channel distances. The distance of the Pt gate to the GaInAs channel was therefore confirmed through high-resolution cross-sectional scanning transmission electron microscopy analysis. The results presented here reveal that both the suitable ramp rate and the sink-in ambient are necessary to achieve a fully sunken Pt gate.