Design of a parallel self-timed adder by using transmission gate logic style

In this paper, the design of a parallel self-timed adder by using transmission gate logic style was implemented for multi bit binary addition. Parallel Asynchronous Self Timed Adder (PASTA) is designed by using transmission gate based on recursive formulation. Multiplexer is used in this design for avoiding difficulties of interconnections. The operation is parallel to avoid carry chain propagation. In carry-look ahead adder due to carry chain propagation there is a problem of high fan-in and fan-out. In this PASTA completion detection unit is present for connecting all carries to avoid high fan-out. A high fan-in is unavoidable for asynchronous logic through transistors is connected in parallel. The simulation of the proposed design is carried out by using cadence spectra circuit simulator. The simulation results of proposed model attain better power consumption and reduction in number of transistors and results are verified with proposed technique in 180nm, 90nm and 45nm.