Saving Energy on Processor Micro-Architecture Level for Big Data Stream Mobile Computing

To meet the challenges of big data stream mobile computing, several low power methods are proposed on processor micro-architecture level to improve the energy efficiency in the process of communication, which includes: (1) A heterogeneous variable-length VLIW architecture with power saving mode is introduced to reduce data path power. (2) Concatenating operation is employed to forward intermediate results to consuming units directly to reduce register file access power. (3) Hardware based loop optimization joint with flexible vector load/store address generation mode is proposed for lower memory access power consumption. (4) Reducing copy/movement operations of vector register file (VRF) for low access power. (5) Avoiding short-lived values (SLVs) to be written back to reduce power consumption by buffer-aided VRF. The experiment results show these low power technologies can reduce overall power dissipation about 26% over baseline.