New Integrated Crystal Oscillator Design With Improved Robustness Against ESD Disturbances in Operation

This paper investigates the influence of electrostatic discharge (ESD) in operation on an integrated Pierce crystal oscillator for clock signal generation. We show that ESD, which has been capacitively coupled into the circuit, can cause temporary suspension of the clock signal. We analyze the coupling path and in addition we present a new, more robust crystal oscillator design for integrated circuits (IC) and compare design parameters, e.g., ESD compliance, power consumption, chip area, and phase noise. Simulations are confirmed by measurements on test circuits.