Systematic Approach to Design High Power FPGA Package for Current-Carrying Capability

This paper describes a systematic approach to design FPGA package for current carrying capability. As we examine silicon, interposer, and package, the profound challenge is found to meet the lifetime of high power device against the greater chance of failures owing to worsen electro-migration in every interconnect level. Our approach consists of practical methodologies to estimate current distribution and to calculate accumulated failure rates from an entire substrate including BGA ball, micro-via and plated through hole. The approach reported here allows lifetime calculation from the progressive failure of individual BGA over the different time span. In the end, we apply the methodology to a 200A high power design achieved with the most efficient ball count that meets lifetime specification.