Analysis of System-Level Reliability of Single-Chip Glass BGA Packages with Advanced Solders and Polymer Collars

Emerging high-performance computing systems have been aggressively driving advances in packaging technologies to meet their escalating performance and miniaturization needs. Large, high-density 2.5D silicon interposers have gained momentum with the recent split-die trend but face critical reliability challenges at board-level that are addressed by introducing an additional organic BGA package between interposer and board. Glass substrates have emerged as a promising alternative owing to the superior electrical properties, sub-5μm lithographic capability and tunable CTE of glass that enables direct SMT assembly to mother boards among other advantages. This paper investigates board-level reliability of single-chip glass BGA packages, 18.5mm × 18.5mm in body size and 100μm in thickness at 400μm BGA pitch. A parametric finite-element analysis was performed to extract the optimum glass CTE for balanced chip-and board-level reliabilities. Innovative doped solder materials and strain-relief mechanisms were evaluated to improve board-level reliability with minimum system-level impact. Daisy-chain test vehicles with low (3.3ppm/K) and high (9.8ppm/K) CTE glass substrates were fabricated and assembled at chip and board levels by Cu pillar thermocompression bonding and standard SMT reflow, respectively. Assemblies with different BGA solder alloys, SAC105, SAC305 and Indium's Mn-doped SACm™, were subjected to thermal cycling test according to JEDEC standards. Comprehensive failure analysis was performed to evaluate fatigue life improvements with advanced interconnection materials and conclude on scalability of glass substrates for high-performance applications.