Gate-to-source/drain fringing capacitance model with process variation of MOSFET in 40nm generation

In this paper, a semi-analytical model for the gate-to-source/drain fringing capacitance (Cf) of MOSFET including process variations is presented. Cf is defined as a layout-dependent parasitic capacitance separated from gate-to-contact capacitance (Cco), and is composed of several dual-k perpendicular-plate capacitances. Layout-dependent coefficients such as gate to contact space (CPS) and contact to contact space (CCS) are found to significantly influence Cf. According to the silicon data, Cf model is optimized including the process variation. The errors between silicon data and simulation are under 15%. The proposed model can improve the precision for digital and RF circuit simulation in sub-nanometer technology generation.