A three stage, fully differential D-band CMOS power amplifier

In this paper, the design and implementation of a three stage fully differential D-band power amplifier in 65nm CMOS technology is demonstrated. By using the capacitive neutralization technology and inter-stage matching networks based on transformers, this power amplifier achieves a peak power gain of 16.8dB and 7.9dBm saturated output power at 140GHz. The power amplifier occupies 0.2mm
²
chip area (including pads). And the power consumption is 80mW from a 1.2V supply voltage (2V for the cascode stage ).