A quasi-closed-loop auto frequency calibration circuit for PLL

A quasi-closed-loop auto frequency calibration circuit for PLL with 180nm CMOS process is designed in this paper. The optimized structure could avoid the problem of start-up trap appearing in conventional closed-loop structure. The binary search method is adopted to reduce frequency sub-band searching time, which could accelerate the PLL locking process. The circuit is simulated by Spectre, and the results show that the total locking time of PLL is approximately 8μs, and the auto frequency calibration time is 4μs.