A single-chip CIF 30-Hz, H261, H263, and H263+ video encoder/decoder with embedded display controller

A single-chip video codec with embedded display controller for videotelephony applications is described. It encodes and decodes simultaneously up to 30 CIF pictures per second according to video-conferencing recommendations H261, H263 (all five options), and H263+ (six additional options). The die area is 132 mm/sup 2/ in a 0.35-/spl mu/m technology, and the power consumption is 1.4 W. The chip uses a distributed dedicated multiprocessor architecture; where computation-intensive functions are done by dedicated hardware, and where picture quality or standard dependent parts are done in software on dedicated programmable processors. Main architectural choices are discussed, and emphasis is put on hardware/software partitioning and codesign.