A 1.2 V, 0.84 pJ/conv.-Step ultra-low power capacitance to digital converter for microphone based auscultation

In this paper, we propose a novel Capacitance to Digital Converter (CDC) architecture using a second order continuous time delta-sigma modulator (CT-ΔΣM) with multi-bit quantization. The proposed architecture embeds a Capacitance to Voltage Converter (CVC) in the delta-sigma loop for improving the dynamic range and the energy efficiency of the CDC. VCO-integrator/multi-bit quantizer, used as one of the loop filters, helps in reducing the swing at the output of CVC. Measurement results from a test chip fabricated in 0.18 μm CMOS technology show that the CDC achieves 13-bit resolution with a measurement time of 0.125 ms while consuming only 42 μΑ at 1.2V. This corresponds to a state-of-the-art figure-of-merit (FoM) of 0.84 pJ/conversion-step.