Design and comparative analysis of low power 64 Bit SRAM and its peripherals using power reduction techniques

Today is the era of portable electronics where maximum functionality is embedded in the tiny chips. Advancement in deep submicron technology, has spurred the race of enhancing the number of transistors on VLSI chips. RAM and especially cache memory is considered to be the major part of any computing device, so power dissipation of memory is of major concern for VLSI design. Hence the major challenge is to design the memory cells which consume low power as compared to the conventional cells. Three various scheme are proposed in this paper for reduction of power in SRAM and these are Charge Recycling, Power Gating and low power design of peripherals. In this paper these techniques are implemented successfully on 45 nm technology. A 1/10th reduction in average power in sense amplifier design is achieved and power reduced in decoder design is 30.08 %. Power reduction achieved for 64 bit SRAM using CR and MT scheme is 20.84%, 47.79% and 49.79% respectively for standbyx, read and write cycle.