A 0.9 V operation 2-transistor flash memory for embedded logic LSIs

A novel 2-transistor flash memory cell is proposed to meet the read performance of mask ROMs. A very low 0.9 V nonword-line-boosting read operation is successfully achieved by employing a novel 2-transistor channel F-N program and channel F-N erase NOR (2-Tr CCNOR) flash memory architecture. We realize a low power program/erase scheme and high reliability by utilizing hole-free channel F-N tunneling with a simple memory cell structure and process.