Electrical performance of directly attached SiC power MOSFET bare dies in a half-bridge configuration

The demand for high-efficiency power converters is increasing continuously. The switching losses are typically significant in power converters. During the switching time, the component is exposed to a considerable voltage and current causing power loss. The switching time is limited by parasitic inductance produced by traces and interconnections inside and outside the package of a device. Moreover, the parasitic inductances at the input-terminal together with the Miller capacitance generate oscillations causing instability and additional losses. In order to eliminate the package parasitic inductance, four 1.2kV SiC-MOSFET bare dies, two in parallel in each position, were directly attached to a PCB sandwich designed as a half bridge. The obtained structure forms a planar power module. From ANSYS Q3D simulations it was found that the parasitic inductance between drain and source for each transistor in the proposed planar module could be reduced 92 % compared to a TO247 package. The planar module was also tested as a dc-dc converter. Switching waveforms from these experiments are also presented.