Modeling a Si homojunction SOI-Tunnel FET with configurable voltage difference on gates

The impact of gate voltage differences on the performance of the novel n-type silicon homojunction SOI-Tunnel FET is studied. Based on numerical simulation results using Synopsys Technology Computer-Aided Design (TCAD), the higher on-current and the ultra-low off-current are observed as compared to that of a conventional SOI-Tunnel FET. The analysis of energy band corroborates that gate voltage differences can revamp the potential barrier in the channel region, which can in turn modulate the drain current.