Offset Analysis and Design Optimization of a Dynamic Sense Amplifier for Resistive Memories

The input-referred offset of a dynamic latch-based sense amplifier for resistive memories is extensively analyzed. This circuit is modeled using both small and large signal analysis, in order to evaluate mismatch effects and to support design robustness to process variations. Effect of various design parameters on offset are studied and reported. It is shown that load capacitance has a profound effect on the sense amplifier offset. Design optimization is then proposed thanks to this analysis, resulting to an input-referred offset (simply called offset in the rest of the paper) down to about 200 Ohms for one sigma variation with 20fF applied load capacitance.