Behavioral modeling of a sensor interface circuit including various non-idealities

In modern CMOS processes, several non-ideal influences affect the functionality of integrated circuits. In order to analyze and reduce these influences, time intensive circuit simulations are performed at transistor level. Although numerous non-idealities are considered in such simulations, they cannot be analyzed separately since they are inherent parts of the transistor models and cannot be faded out. In this work, a solution to this problem is presented: the use of Verilog-A/MS behavioral models in combination with Response Surface Modeling. Since error sources can easily be switched on and off in these models, their influence on circuit parameters can be examined individually. Moreover, the required simulation time is drastically reduced by using these models. A 65nm CMOS sensor interface is selected to demonstrate the advantages of the introduced approach. The interface is transferred from transistor to behavioral level before both circuit representations are compared in various simulations.