Design of a low power wide range phase locked loop using 180nm CMOS technology

This paper presents the design of a third order, low power fully integrated phase-locked loop (PLL) with a wide range of 1.7GHz to 2.5GHz using UMC 180nm CMOS technology. The model designed has a conventional Integer-N PLL based frequency synthesizer architecture with design modifications to the voltage controlled oscillator (VCO). The post layout results reveal that the jitter of the PLL after it has settled at a frequency of 2GHz at 14.1μs is around 35.26ps. The total power consumption of this PLL is 274.346uW when operated on 1.4/1.8V at an output frequency of 2GHz. This design takes an area of 0.11862 mm
²
and can be used for ZigBee applications.