A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization

This work describes the implementation of a DCT (Discrete Cosine Transform) chip targeted to low power video (MPEG2 MP@ML) and still image (JPEG) applications. The chip exhibits two innovative techniques for arithmetic operation reduction in the DCT computation context (MSB rejection and row-column classification) along with standard voltage scaling techniques such as pipelining and parallelism.