Integration challenges of low temperature BEOL interconnects

We present the first exploratory low temperature, lower than standard back-end-of-line (BEOL) interconnects temperature in CMOS. The approach poses several challenges such as undercut in pad via, photo resist residue defects post Aluminum (Al) etch and patch defects post passivation etch. We achieved the electrical targets and met reliability specifications of passivation integrity test (PIT), stress migration (SM), electro migration (EM) for high aspect ratio (HAR) dual damascene via, and pad via interconnects.