Z-scan based lifting architecture for a 2-D discrete wavelet transform

It is a brief explanation of an efficient z-scan based lifting architecture for a 2-D discrete wavelet transform was introduced. It present a new algorithm of lifting steps based on flipping technique for efficient hardware architecture with the simple control path. Here the data was optimized by parallel computations of pipeline operations. It reduces the critical path to one multiplier delay for achieving 100% hardware utilization. The proposed method is repeatable and use five transposition registers. It can be folded for minimizing data path to six multipliers and eight adders without disturbing the critical path. The hardware implementation of field-programmable gate-array target indicates better efficiency.