An arrayed test structure for transistor damage assessment induced by circuit analysis and repairing processes with back-side-accessing Focused Ion Beam

We propose an arrayed test structure to assess the damages of metal-oxide-semiconductor field-effect transistors (MOSFETs) exposed under back-side LSI processes, such as by Focused Ion Beam (FIB). Back-side process with FIB is becoming essential to analyze and repair modern LSI chips, to avoid processing through many metal layers with dense wiring and dummy patterns. To access transistors from back-side, however, FET active region must be cropped out and that may cause damage to transistor characteristics. Our test structure consists of 2-D-arrayed MOSFETs. The impact by the back-side process on various conditions can be visualized as I-V characteristics change. The test structure was used with several FIB back-side processes and visualized the damages as threshold shift. The measurement indicated the importance of mixture of fast-and-isotropic etching and slow-and-anistoropic etching to miminimize electrical damage.