A pipelined architecture for user-defined floating-point complex division on FPGA

A novel high performance pipelined implementation architecture for user-defined floating-point complex division is presented. The major part of the proposed algorithm is derived from conventional Goldschmidt division algorithm. This paper first describes related user-defined floating-point arithmetic based on FPGA. Then the core of the complex division: (A+jC)/B is implemented based on the proposed modified Goldschmidt algorithm. Finally, the proposed fully pipelined implementation architectures is co-simulated by Modelsim and Simulink, and it is synthesized on FPGA using Verilog and VHDL. Our simulation shows that the proposed implementation performs better than the conventional schemes in reducing the consumption of hardware resources.