An efficient VLSI architecture design for integer DCT in HEVC standard

In this paper, we design new efficient VLSI architecture for Integer Discrete Cosine Transform (DCT) included in the last new High Efficiency Video Coding (HEVC) standard. The proposed architecture has 4×4/8×8/16×16/32×32 Transform Units (TUs) operating in a parallel way to calculate two dimensional (2D) integer DCT using one block 1-D DCT and one transpose memory. Transform 1D is first calculated and the corresponding transform is stored in a memory. These stored data are secondly used to achieve the 2D DCT transform, using the same block for the first calculation for 1D. In addition, this architecture is based on shift and adder instead of the multiplication. The implementation was performed on the Xilinx Artix-7 (Zynq-7000) FPGA, the proposed accelerator hardware 2-D integer DCT takes 34421 slice LUTs, 8729 slice registers and the maximum achievable clock frequency for the proposed implementation is 289 Mhz. Finally, this design can be used to process the 30 frames for 8K video sequence and up to 120 frames per second for 4K.