A 100 mW 10 bit 100 MS/s all CMOS ADC

A l0-bit 100 MS/s ADC based on a pipelined architecture has been design for fabrication in a 0.35 um CMOS process. The complete converter includes an on-chip reference, an input buffer and sample-and-hold. The ADC core operates from a 2.7 V to 3.3 V supply and dissipates 93 mW when operated with a 3 V supply.