Parameters study of thermomechanical reliability of board-level fan-out package

Smaller form factor, thermal/electrical efficiency and low-cost manufacturing are characteristics of the wafer level chip scale package (WLCSP) which had been widely used by market demand especially in handheld and portable applications in past several years. However, the challenge of board level reliability tests such as drop test, thermal cycling loading test to limit package size for higher I/O density application. Fan-out (FO) technique is developed to broaden the package area and to accommodate an increasing I/O density. The molding dies into an architectural wafer with epoxy molding compound (EMC) by re-constitution (Recon) process. In this study, three-dimensional computational aWLP (advanced wafer level package) model was developed for analyze solder joint reliability during TCoB (thermal cycles on board) testing. Structural factors of thickness of package and dielectric, size of die and package were selected to evaluate correlation with solder joint reliability. The result predicted by finite-element model (FEM) indicated that the lower package flexural rigidity (thinner package), smaller die size, stress buffer enhancement (thicker dielectric thickness), and larger package size would be enhance solder thermal cycling reliability. Examining the effect of each control factor, we notice that the ratio of die size over package size is the most important control factor.