Resolving Endurance and Program Time Trade-Off of 40nm TaOx-Based ReRAM by Co-Optimizing Verify Cycles, Reset Voltage and ECC Strength

Trade-off between reliability and program time in 40nm TaO
_x
-based Resistive random access memory (ReRAM) is experimentally investigated. By evaluating bit error rate (BER) and the current distributions, the complicated trade-off among Set/Reset cycles, reset voltage (V
_RESET
) and with or without verify are investigated. At lower Set/Reset cycles, the current window is enhanced by introducing Set/Reset cycles and increasing V
_RESET
. However, at higher Set/Reset cycles, the excessive stress caused by the verify and high V
_RESET
increases BER. Because of this "twisted" characteristics, verify should not be performed at higher Set/Reset cycles. To explain these complicated errors, the physical model based on oxygen vacancy (Vo), diffusion is described. Finally, the system-level solution to minimize errors by dynamically co-optimizing ECC strength, verify cycles and the Reset voltage based on Set/Reset cycles is proposed.