Synthesis of a microelectronic structure of a specialized processor for sorting an array of binary numbers

Methods for graphical representation of algorithms of sorting arrays of binary numbers were analyzed. Improved schematic solution for structure development and components of specialized processor for sorting an array of binary numbers by “bubbles” method was represented. As a result, high-performance structures of specialized processors for sorting an array of binary numbers on FPGA were synthesized. System characteristics of hardware and time complexity of this class of processors targeted at microelectronic implementation in structure of embedded systems were calculated.