Normally-Off LPCVD-SiNx/GaN MIS-FET With Crystalline Oxidation Interlayer

Developing effective technique to protect the etched-GaN surface from the degradation in a high-temperature (i.e., at ~ 780°C) process, such as low-pressure chemical vapor deposition (LPCVD), is essential for fabricating normally-off GaN MIS-FETs with high-quality dielectric/GaN interface and highly reliable gate dielectric. In this letter, we developed an approach of obtaining such a protection layer using oxygen-plasma treatment followed by in situ annealing prior to the LPCVD-SiN
_x
deposition. A sharp and stable crystalline oxidation interlayer (COIL) between the LPCVD-SiN
_x
and etched-GaN was successfully formed. The LPCVD-SiN
_x
/GaN MIS-FETs with COIL deliver normally-off operation with a V
_TH
of 1.15 V, small ON-resistance, small hysteresis, and thermally stable V
_TH
.