Electrical stability impact of gate oxide in channel implanted SiC NMOS and PMOS transistors

Summary form only given. The complete presentation was not made available for publication as part of the conference proceedings. Operation of SiC MOSFETs beyond 300°C opens up opportunities for a wide range of CMOS based digital and analogue applications. However the majority of the literature focuses only on the optimization of a single type of MOS device (either PMOS or more commonly NMOS) and there is a lack of a comprehensive study describing the challenge of optimizing CMOS devices. This study reports on the impact of gate oxide performance in channel implanted SiC on the electrical stability for both NMOS and PMOS capacitors and transistors. Parameters including interface state density (D
it
), flatband voltage (F
FB
), threshold voltage (V
TH
) and effective charge (N
EFF
) have been acquired from C-V characteristics to assess the effectiveness of the fabrication process in realising high quality gate dielectrics. The performance of SiC based CMOS transistors were analyzed by correlating the characteristics of the MOS interface properties, the MOSFET 1/f noise performance and transistor on-state stability at 300°C. The observed instability of PMOS devices is more significant than in equivalent NMOS devices. The results from MOS capacitors comprising interface state density (D
it
), flatband voltage (F
FB
), threshold voltage (V
FB
) for both N and P MOS are in agreement with the expected characteristics of the respective transistors.