Low Power FinFET based 10T SRAM cell

Memory occupies more than 70 percent of area in today's system on chip and the trends continue to be increases in coming years. As the technology is scaling the bulk MOSFET faces various challenges which lead to increased leakage. Below 32nm technology, FinFET is the most promising substitute to bulk CMOS technology because of reduced short channel effect. The proposed 10T SRAM cell is designed using MOSFET, FinFET at 16nm technology node and its performance parameters such as power, delay, Power Delay Product (PDP), leakage current and Static Noise Margin (SNM) are compared with conventional 6T SRAM cell.