Real-time brain activation detection by FPGA implemented adaptive algorithm

This paper proposes a computationally efficient embedded system, implemented on field programmable gate arrays (FPGA), for real-time brain imaging. An RS-232 core is employed to obtain the brain data from a functional near-infrared spectroscopy (fNIRS) imaging modality on sample basis. A 32-bit floating point core (IEEE754) is developed on FPGA to manipulate floating point data with precision. Recursive least-squares estimation (RLSE) core is implemented on FPGA to facilitate computationally-efficient parallel adaptive processing (filtering) of multiple channels for real-time brain-activity estimation, for the first time as per our knowledge. The brain activation model and the methodology for its parameters' estimation by RLSE is depicted from Aqil et al., 2012 [2] and implemented on FPGA. The proposed embedded real-time methodology is demonstrated by instantiating eight RLSE cores on an FPGA board (Spartan-6 LX150T Development Kit) followed by its validation with an open source fNIRS dataset. The real-time results obtained with the proposed embedded system matches with the previously reported online results. Multiple RLSE cores can be instantiated, depending on the available resources of the FPGA, to process multiple channels concurrently.