Experimental Investigation of ${C}$ – ${V}$ Characteristics of Si Tunnel FETs

This letter presents an experimental capacitance-voltage C-V analysis for Si p-tunnel FETs (TFETs) fabricated on ultrathin body at various frequencies and temperatures. The capacitance distribution in TFETs is quite different compared with MOSFETs, due to different inversion charges partitioning between source and drain. Contrary to predictions from simulations, we provide experimental evidence for the first time that the contribution of the gate-to-source capacitance C
_gs
to the total gate capacitance is much larger than expected, and even comparable to the gate-to-drain capacitance C
_gd
at higher V
_ds
and V
_g
. Comparable values of C
_gs
and C
_gd
would imply that the Miller capacitance effect in TFETs-based circuits is less pronounced as predicted in simulations.