On-Chip Two-Tone Synthesizer Based on a Mixing-FIR Architecture

A low-distortion current-steering two-tone sinusoidal signal synthesizer based on a mixing-finite impulse response (FIR) architecture is proposed. The proposed robust synthesizer adopts only digital blocks. It implements a two-stage cascade FIR harmonic cancellation technique that generates a single tone quasi-sinusoidal waveform and suppress the odd-order harmonics up to the 21st order. Differential-mode circuitry and a 50% duty cycle clock are also utilized to cancel the even-order harmonics. The single-tone signal is further up-converted to the desired local oscillator (LO) frequency band, thereby producing the desired two-tone sinusoidal signals. The proposed synthesizer contains a current mirror array implementing the FIR tap coefficients. Accuracy is enhanced using dynamic element matching. The other building blocks consist of a 24-phase clock generator, a current combiner, and a passive mixer with bootstrapped MOS switches. This two-tone synthesizer can be used to conduct a linearity built-in self-test. It is fabricated in 130-nm standard CMOS technology, occupying a 0.056-mm
²
silicon area. Measurement shows better than -68 dBc third-order intermodulation (IM3) below 480-MHz LO frequency without calibration. For the LO frequency <;76.8 MHz and the two-tone difference <;2 MHz, an IM3 better than -75 dBc can be achieved. The imbalance between the two-tone amplitudes is measured <;0.1 dB across the whole frequency range from dc to 1 GHz.