Modeling and simulation study of short gate TFET architecture considering the impact of mobile charge carriers

In this work, an analytical surface potential model to capture the benefits of gate underlap TFET over conventional p-i-n TFET architecture has been developed. The model has been derived in all three operational regimes considering the mobile charge carriers. Impact of gate and drain bias along with metal gate work function tuning over the potential profile has been studied extensively through the analytical model. Additionally, simulations have been performed to investigate and discuss how the channel potential plays a significant role to control the tunneling barrier width at drain/channel junction and affects the charge conduction mechanism. The modeled results have been validated through exhaustive simulations performed using ATLAS.