A flexible and expendable neuroimage processor architecture

An analog versatile neuroimage processor (VNIP) architecture is proposed here. VNIP can process various types of neural network and image processing structures, without any hardware modification. The structure allows unlimited expansion of network size and the compensation of process variation. The proof-of-concept chip is implemented, using a combination of continuous-time multiplier and switched-capacitor techniques. The throughput is 12/spl times/10/sup 6/ synapses/s.mm/sup 2/ and the energy consumption is 10/sup -9/ J/synapse. A test chip was fabricated, using a 1.2-/spl mu/m double-poly CMOS process and tested, verifying the flexibility and expandability of the architecture.