Architecture, on-chip network and programming interface concept for multiprocessor system-on-chip

This paper presents a system architecture, data communication scheme and application programming interface model or concept for a multiprocessor system based on a network-on-chip (NoC) platform. Each processing node connected to a mesh node has its own local (instruction and data) memory portion, and a global (shared) memory portion. The introduced communication scheme gives only a minimum overhead in order to offer direct memory-to-memory data transfer. Each processor can make direct message delivery to another processor (producer initiated), or make a request to copy memory blocks from a remote processor (consumer initiated). The complete data transmission is handled by the network interface and a special memory controller. The network interface managed by the specialized memory controller can directly access the shared memory portion. Thus the processing node can continue its normal operation and will be not blocked during the data transfer process.