Suppressing Single Transistor Latch Effect in Energy Efficient Steep Switching Junctionless MOSFETs

In this paper, we present an innovative approach to suppress the Single Transistor Latch (STL), a critical limiting phenomenon, in steep switching n-type Silicon (Si) and Germanium (Ge) Double Gate (DG) Junctionless (JL) transistors. The single transistor latch effect, which can limit the operation of the device, can be effectively controlled by sidewall spacer engineering through the optimization of permittivity and thickness, and extend the usable range of device operation for dynamic memory applications. It is shown that through appropriate choice of sidewall spacer parameters, the extent of Impact Ionization (II) occurring in the device can be reduced through the influence of the vertical fringing field while still preserving the sharp increase in drain current which governs the hysteresis window at scaled gate lengths (50 nm) and lower supply voltages (0.9 V). A low permittivity wider sidewall spacer or high permittivity narrow spacer material is optimal for preserving device operation and avoiding STL. The work provides valuable insights into device design and demonstrates the significance of selecting appropriate sidewall spacer parameters as a way forward to overcome STL.