Tutorial T8: Communication Infrastructure for Future Exascale Processors

Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. Current commercial System-on-Chip (SoC) designs integrate an increasingly large number of predesigned cores, and their number is predicted to increase significantly in the near future. These stateof- the-art commercial SoC designs with a large number of intellectual property (IP) blocks, commonly known as cores, on a single die are made feasible by the continuing progress and integration levels in silicon technologies. The growing complexity of integration as well as aggressive technology scaling introduces multiple challenges for the design of such big multi-core SoCs. An important feature of such Multi-Processor SoCs (MP-SoC) is the interconnection fabric, which must allow seamless integration of numerous cores performing various functionalities. Networks-on-Chip (NoCs) have garnered significant interest as communication backbone for multicore processors used across a wide range of fields that demand higher computation capability. Wireless NoCs (WNoCs) by augmenting single hop, long range wireless links with wired interconnects; offer the most promising solution to reduce multi-hop long distance communication bottlenecks and opens up innumerable possibilities of topological innovations that are not possible otherwise. In this tutorial, we will elaborate the promises and challenges associated with WNoCs. We will also highlight how on-chip wireless can help in resolving different housekeeping issues related to future many-core processors.