SAD and SSE implementation for HEVC encoder on DSP TMS320C6678

High Efficiency Video Coding is the latest video standard aiming to replace H264/AVC standard by improving significantly the coding efficiency and the compression performance which allows HEVC to be mostly suitable for high-definition videos for multimedia applications. However, the encoding process requires a high computational complexity that needs to be alleviated. Hence, the paper proposes a software implementation of HEVC encoder and an optimized architecture on single core DSP TMS320C6678 to perform the rate distortion optimization (RDO) for mode decision procedure. The goal is to use single instruction multiple data (SIMD) operations and data level parallelism in order to optimize the Sum of Absolute Differences (SAD) and Sum Square Error (SSE) engines. The performance of the proposed implementation shows more than 88% improvement in terms of cycle cost for the distortion functions computation and the encoding speed of the proposed optimized HEVC encoder is accelerated by approximately 24% compared to the HEVC reference model (HM12.0) software with slight loss of coding efficiency.