Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units

In this paper, we propose a new approach to use a residue number system (RNS) to design an arithmetic unit to parallelize execution of addition and multiplication. The chosen RNS is defined by a moduli set composed of one larger even modulus 2k and all remaining moduli of the type 2
ⁿ
- 1, selected to fit into the word size of a typical general-purpose processor, e.g., 32 or 64 b. The RNS operations are implemented in hardware, except for the reverse conversion, which is implemented in software, allowing not only to save hardware area but also offering the ease of run-time changing of the dynamic range, which in turn can result in reducing both power consumption and execution time. Simulation experiments were performed on synthesized seven-operation arithmetic units with varying dynamic range for three applications: constant-coefficient filtering, matrix multiplication, and large Montgomery multiplication. The results show that thanks to smaller modular multipliers, RNS arithmetic units have smaller both area and delay, and, consequently, they allow to achieve up to over 20% energy saving for a constant-coefficient filter application, up to over 28% for the matrix multiplication, and up to 27% for Montgomery multiplication, compared with executions using a positional arithmetic unit.