Design & optimization of Parallel Self timed Adder using advance technique

Transistor count is the primary concern which affects the design complexity of the circuit. For such submicron CMOS technology area, power dissipation and speed are very important factors for high speed and low power applications. An Asynchronous Parallel Self-timed Adder (PASTA) implemented by using Gate Diffusion Input (GDI) Technique. This advanced technique used to reduce area, power and transistor count effectively as compare to other CPL, DPL and conventional CMOS design. PASTA design uses multiplexers along with half adders. For bits that do not need any carry chain propagation the operation is parallel. Thus, not requiring a speedup circuitry. According to carry signal, completion detection unit enables the selection line of MUX which will decides the input to half adder. Simulation study have been performed using Tanner EDA that verifies the correctness of the proposed technique executed in 90nm.