4:2 and 5:2 Decimal Compressors

Decimal compressors are essential components for partial product addition facilitating decimal multipliers. In this paper improved design and architectures of 4:2 and 5:2 high speed compressors have been reported. Binary full adders, optimized unconventional (non binary coded decimal) recoding scheme, have been used to implement basic digit compressor. Cascaded operations of the basic digit compressors have been used to implement the higher order like 4:2 and 5:2 decimal compressors which ensures the high speed operations. Configurations of decimal compressors (4:2 and 5:2) have been prototyped and simulated to evaluate performance parameters like speed (propagation delay), power dissipation, power-delay product and energy delay product. The simulation have been carried out in Cadence Specter using 90nm technology reveled the propagation delay of the resulted compressors were ~41ns and ~61ns respectively. Moreover reported architecture offered ~38% improvement in speed compared with the best reported architecture so far for 5:2 compressor.