Behavioral modeling to circuit design steps of an injection locked CDR in 0.18µm-CMOS

In this paper the design, simulation and measurement procedure of injection locked clock and data recovery(CDR) circuit is discussed. The non-idealities of the CDR circuit such as power supply noise and lock detection are modeled behaviorally using Verilog-A. The required CDR specifications can be extracted in a very short period of simulation time with the designed behavioral model. The designed CDR features with full speed, dual loop, coarse and fine tuning and injection locked technology. The proposed CDR is fabricated with SMIC 0.18um 1P6M process and consumes 36mW from a single 1.8 V supply. Measured results show that the 250Mbps input NRZ signal could be correctly recovered with 2ps root-mean-square jitter.