Low power multi threshold 7T SRAM cell

Technologies like Internet of Things (IoT) are bringing new challenges to IC design, where power dissipation is desired to be less for portable devices. Further scaling of devices for portability requires reliable memories which can be operated at lower voltages. In this paper, a modified 7T SRAM cell has been proposed with high static noise margin. The proposed 7T RAM has been compared with conventional 6T SRAM and LP7T SRAM in terms of static noise margins and power. The SNM results show an increase of 48% and 78% over the standard 6T for writing 0 and 1 respectively, 122% increase in RSNM when compared to standard 6T SRAM bit cell and slightly better results than LP 7T bit cell for RSNM and Hold SNM when simulated in Cadence virtuoso using 65nm CMOS technology. The proposed design uses 50% and 16.5% less power compared to standard 6T SRAM for dynamic write and read respectively. The Monte Carlo simulation on process and mismatch parameters shows a very small deviation.