FPGA-based convolutional neural network accelerator design using high level synthesize

Convolutional Neural Networks are well known for their outstanding results in recent years in computer vision applications. Two hardware architectures for implementing these networks are proposed. The first one is more application specific which is suitable for smaller convolutional networks and the second one is more extendable and can be easily used for larger networks. A new method for computing hyperbolic tangent activation function is proposed to reduce computation time. LeNet convolutional network architecture is implemented to recognize handwritten digits using MNIST dataset as a sample. With the proposed architectures, it is indicated that latency is reduced while maintaining accuracy. Experiments are done on Xilinx Zynq FPGA using High Level Synthesis.