Optimized memristor-based ripple carry adders

This work presents improved implementations of memristor-based ripple carry adders using three different approaches: the IMPLY operation, hybrid-CMOS gates, and threshold gates. The designs are optimized by performing parallel operations, leveraging computational redundancies, and recognizing Boolean simplifications. The proposed IMPLY N-bit ripple carry adder decreases the area by 2N-1 components and latency by 3N-1 as compared to the previous state-of-the-art. The hybrid approach improves upon the area in prior work by 4N memristors and 12N MOSFETs while maintaining the same delay. The threshold gate approach is novel and requires only N+1 gate delays and 7N memristors.