Nonlinear modeling of GaAs FET parasitic resistances

An analytical model for the parasitic resistance of MODFET's has been developed. The simulation results for the D.C. characteristics obtained when this model is used have been found to be in good agreement with the experimental data. This model shows that as the drain current, increases, the parasitic resistance increases which explains one of the effects responsible for the transconductance compression phenomenon in MODFET's. Using this parasitic resistance model improves the overall device model prediction, especially in high speed and microwave applications.