High-speed VLSI implementation of reduced complexity sequence estimation algorithms with application to Gigabit Ethernet 1000Base-T

This paper compares reduced complexity sequence estimation (RCSE) algorithms in terms of SNR performance, VLSI implementation, hardware complexity and critical path. A novel architecture is presented which reduces the hardware complexity of RCSE and relaxes the critical path problem. This architecture can be used to implement RCSE for Gigabit Ethernet 1000Base-T.