High-Performance Split-Gate-Enhanced UMOSFET With Dual Channels

This paper presents an optimized split-gateenhanced trench MOSFET with dual channels (DSGEUMOS). The 2-D device simulator ATLAS is used to investigate the characteristics of the proposed structure. When compared with the conventional SGE-UMOS, the optimized device shows a significant reduction in the specific on-resistance (RON-sp) at a breakdown voltage of 120 V, which is due to the adoption of an additional p-type well region. Furthermore, the proposed structure can also enhance the single-event burnout (SEB) survivability. Based on the DSGE-UMOS, the hardened DSGE-UMOS (an n-type buffer layer is added between the epitaxial layer and substrate layer) is also investigated that the addition of the buffer layer can improve the SEB performance a lot.